In a successive approximation register (SAR) analog-to-digital converter, capacitors in a capacitor array are charged to an instantaneous value of an analog input signal voltage at a sampling instant by operation of a sampling switch. To lock in the value of the analog input signal voltage at the sampling instant, the sampling switch is opened. The locked-in value of the analog input signal voltage may be referred to as the sampled analog input voltage. During a subsequent analog-to-digital conversion process, a plurality of conversion switches connected to the capacitors are controlled to effectively generate a series of comparison voltages. The comparison voltages are successively selected, generated, and compared to the sampled analog input voltage to determine whether the sampled analog input voltage is higher or lower than each generated comparison voltage. Each new comparison voltage in a series of comparison voltages is based on comparisons made of the sampled analog input voltage and previous comparison voltages in the series. A series of comparison voltages may start with a first comparison voltage that is in the middle of the highest and lowest values within a nominal analog input voltage range. For example, if the sampled analog input voltage is detected as being higher than the first comparison voltage, a first bit of a digital code is set to a one, and a second comparison voltage in the series of comparison voltages may be generated as the first comparison voltage increased by one fourth (¼) of the span of the nominal analog input voltage range. Continuing the example, if the sampled analog input voltage subsequently is detected as being lower than the second comparison voltage, a second bit in the digital code is set to zero, and a third comparison voltage in the series of comparison voltages may be generated as the second comparison voltage decreased by one eighth (⅛) of the span of the nominal analog input voltage range. By using a successive-approximation algorithm repeatedly (selecting, generating and comparing a series of comparison voltages to successively approximate a sampled analog input voltage) a digital representation of the sampled analog input voltage can be made to have substantially any resolution.
The sampling switch must be substantially non-conductive during the successive-approximation analog-to-digital conversion process, so that the sampled analog input voltage can be preserved and compared accurately to each voltage in the series of comparison voltages. If a junction-isolated MOSFET transistor is used as a sampling switch, its pn junction diodes must not become forward-biased enough to cause substantial conduction when the sampling switch is open, or else the analog-to-digital conversion process may yield an inaccurate result. For example, if the sampling switch is implemented as a junction-isolated NMOS transistor, a pn junction diode formed by a p-doped substrate (or a p-doped well) and an n-doped drain or source region must not become substantially forward-biased during the conversion process. Furthermore, during the analog-to-digital conversion process, a gate voltage applied to the NMOS sampling switch must be sufficiently low to ensure that a conductive channel will not be formed in a p-doped region between the n-doped drain and source regions. These requirements may be difficult to meet when the sampling switch is subject to voltage swings that may exceed an upper and/or a lower boundary of a power supply voltage range.
What is needed is a sampling switch that can be used to accurately sample an analog input signal voltage and remain substantially non-conductive during a period of time when an integrated circuit performs a certain function, for example an analog-to-digital conversion process. What is needed is a sampling switch that can be turned off very quickly, and be controlled to be substantially non-conductive with respect to a predefined voltage range that exceeds a boundary of a power supply voltage range.